1. Field of the Invention
This invention relates to output control circuits.
2. Description of the Prior Art
Conventionally, an IC (integrated circuit) generally called a line driver is commonly known as a drive circuit for driving a logic circuit in a following step or for driving signal (transmission) lines themselves, wherein the line driver IC for driving the above signal (transmission) lines is usually used as an interface IC in order to drive a coaxial cable or the like connecting, for example, a computer and each device (apparatus) such as a peripheral device thereof or the like. An example of such a line driver IC (for example, SN75ALS126 of Texas Instruments Incorporated) is illustrated in FIGS. 8 to 11.
First, an equivalent circuit diagram of the above line driver IC is shown in FIG. 8 to illustrate the connections of each internal circuit element. In this figure, however, only main circuit components are shown for the purpose of illustration; a short circuit protection circuit or the like at the output, for example, is not shown (the same in following examples). Also, a constant current circuit is shown simplified (the same in following examples).
As shown in the figure, the base of an input (PNP) transistor QP1 is connected to an X input terminal (for example, receiving the output of a bipolar type integrated circuit, which is not shown, in a previous step); the emitter thereof is connected through a resistor RP1 to a power supply V.sub.CC ; the collector thereof is connected to ground GND; and the base and the collector of an NPN transistor QP2 are further connected to the emitter of the transistor QP1. A Schottky diode DP1 (the anode is connected to the emitter of the transistor QP2, and the cathode is connected to the base of the transistor QP1) is connected between the emitter of the transistor QP2 and the base of the transistor QP1.
The base of an NPN transistor QP3 is connected to the emitter of the transistor QP2 and to the anode of the Schottky diode DP1; the collector thereof is connected through a resistor RP2 to the power supply V.sub.CC and to the base of an NPN transistor QP5; and the emitter thereof is connected to the base and the collector of an NPN transistor QP4. The emitter of the transistor QP4 is connected to the ground GND.
The collector of a transistor QP5 is connected through a resistor RP3 to the power supply V.sub.CC and through a Schottky diode DP2 (the anode is connected to the collector of the transistor QP5, and the cathode is connected to the base of an NPN transistor QP7) to the base of an NPN transistor Q7 (which has a guard ring and is clamped by a Schottky barrier diode (SBD) between the collector and the base); the emitter of the transistor QP5 is connected through a resistor RP4 to the base of a transistor QP6 and through a resistor RP 5 to the collector of the transistor QP6; and the emitter of the transistor QP6 is further connected to the ground GND.
The collector of the transistor QP7 is connected to the power supply V.sub.CC ; the emitter thereof is connected to the collector of a PNP transistor QP8, to the base of an NPN output transistor QP10 (which has a guard ring and is clamped by a Schottky barrier diode (SBD) between the collector and the base), and to the collector of an NPN transistor QP9, respectively. The emitter of the transistor QP8 is connected to the power supply V.sub.CC ; the base thereof is connected to the base and the collector of a PNP transistor QP11; and the emitter of the transistor QP11 is connected to the power supply V.sub.CC. The base of the transistor QP9 is connected to the emitter of the transistor QP5, and the emitter of the transistor QP9 is connected to the ground GND.
The collector of the output transistor QP10 is connected through a resistor RP6 to the power supply V.sub.CC, and the emitter thereof is connected to a Y output terminal (which is, for example, connected to a bipolar type integrated circuit, not shown in the figure, in a following step). A constant current circuit 1 is connected to the collector of the transistor QP11.
With regard to the operation of each element in FIG. 8, the input transistor QP1 is a transistor to reduce I.sub.IL (I.sub.IL=(V.sub.CC -V.sub.BE(QP1) -V.sub.IL)/(RP1.times.hfe.sub.(QP1)): the "L" level input current, however V.sub.BE(QP1) is the voltage between the base and the emitter of the transistor QP1, and V.sub.IL is the "L" level input voltage, and hfe.sub.(QP1) is the current amplification factor of the transistor QP1); QP2 is a transistor for adjusting V.sub.T (threshold voltage); QP3 is a transistor for internal buffers for a non-inverter; QP4 is a transistor for adjusting V.sub.T ; QP5 is a phase splitter for taking out a signal, which is in an opposite phase to a base signal, from the emitter side of QP5; QP6 is a transistor called active pull-down for improving the response characteristic of the transistor QP9, as a "Baker clamping circuit" which improves the ON/OFF characteristic of QP6; QP7 and QP8 are transistors for driving the output transistor QP10, QP9 is a transistor for pulling out the base electric charge of the output transistor QP10; QP11 is a transistor to constitute a circuit 2, called a current mirror, by being paired with the transistor QP8, in order to flow the current set in the constant current circuit 1 to the transistor QP8; the Schottky diode DP1 is for pulling out the base electric charge of the transistor QP3; and the Schottky diode DP2 is for adjusting V.sub.OH (the "H" level output voltage).
With regard to FIG. 8, the main operation will be described below. The operation as a whole is non-inverted, and when the input is the "L" level, the output is also the "L" level, and when the input is the "H" level, the output is also the "H" level.
First, in the case of the X input changing from the "L" level to the "H" level, when the X input is larger than V.sub.BE(QP2) +V.sub.BE(QP3) +V.sub.BE(QP4) -V.sub.BE(QP1) (about 1.3 V in this example), it switches to the "H" level state, and the input transistor QP1 turns off (the state of the "H" level being in the base). The transistor QP2 turns on when the base thereof is switched to the "H" level by the power supply V.sub.CC through the resistor RP1. Moreover, the transistor QP3 turns on because the base thereof is at the "H" level through the transistor QP2; the transistor QP4 also turns on when the base thereof is switched to the "H" level by the power supply V.sub.CC through the resistor RP2 and the transistor QP3. Therefore, the transistor QP5 turns off when the base thereof switches to the "L" level through the transistors QP3 and QP4. At this time, the transistors QP6 and QP9 are off.
The transistor QP7 turns on when the base thereof is switched to the "H" level by the power supply V.sub.CC through the resistor RP3 and the diode DP2; the emitter current I.sub.E(QP7) of the transistor QP7 flows to the base of the output transistor QP10. Also with the transistor QP9 turned off, the collector current I.sub.C(QP8) of the transistor QP8 also flows to the base of the transistor QP10. Therefore, the output transistor QP10 turns on when the base thereof switches to the "H" level; the Y output (the emitter of the transistor QP10) is switched to the "H" level by the power supply V.sub.CC through the resistor RP6. However, the transistor QP7 is cut off when V.sub.OH (the "H" level output voltage) becomes V.sub.OH =V.sub.CC -(V.sub.F(DP2) +V.sub.BE(QP7) +V.sub.BE(QP10)) (V.sub.F, however, is the voltage drop of the Schottky diode). Thus, the transistor QP10 thereafter turns on only by the current (I.sub.C) of the transistor QP8.
Next, in the case of the X input changing from the "H" level to the "L" level, the operation may be opposite to the above. That is, when the X input is smaller than V.sub.BE(QP2) +V.sub.BE(QP3) +V.sub.BE(QP4) -V.sub.BE(QP1) (about 1.3 V in this example), it switches to the "L" level state, and the input transistor QP1 turns on (the state of the "L" level being in the base). Contrary to the above operation, the transistors QP2, QP3 and QP4 each turn off, and the transistors QP5, QP6, QP7 and QP9 each turn on.
Therefore, with the transistor QP9 passing the current (that is, I.sub.C(QP8)) of the transistor QP8 to the ground GND and pulling out the base electric charge (that is, the base current I.sub.B(QP10)) of the transistor QP10, the transistor QP10 turns off, and the Y output (the emitter of the transistor QP10) switches to the "L" level.
The above described line driver has a very excellent performance in a high speed operation or the like, but various examinations by the inventors show that there is more room for improvement, which will be described below.
Generally, in packaging high speed logic ICs or the like, noise in signal lines or the like must be taken into account; otherwise, circuits may not operate normally because of alternating current noise such as reflection noise, cross talk noise, or the like in signal transmission lines. Depending on the characteristic impedance of the signal transmission paths, the amplitude (size) of the noise, although different, is generally proportional to the signal amplitude and inversely proportional to the rise time (tr) and the fall time (tf) of the output; thus, although the operation in internal circuits of the above line driver or the like is at a high speed, the slew rate (the maximum time change rate of the output voltage) at the output thereof has to be small.
With regard to the slew rate at the output in FIG. 8 described above, the slew rate at the output depends greatly on the characteristics of chiefly the resistor RP3 and the transistors QP5, QP7, QP9 and QP10, which are mostly determined by process conditions in fabrication. That is, with the circuit as in FIG. 8 constituted by using the latest miniaturizing process especially for high speed operation, low power consumption or the like, the switching operation of each element is performed inevitably at a high speed.
At the rise time of the output, as described above, a rising waveform of the output is obtained by passing the currents I.sub.E(QP7) and I.sub.C(QP8) (I.sub.E is the emitter current, and I.sub.C is the collector current) of the transistors QP7 and QP8 respectively to the base of the output transistor QP10; at this time, taking the control of the slew rate into consideration, the rise time tr may be adjusted by setting the resistor RP3 and the constant current value of the constant current circuit 1 in the circuit shown in FIG. 8. At the fall time of the output, however, as described above, a falling waveform of the output is obtained by pulling out the base electric charge of the output transistor QP10 by the transistor QP9, but the current which flows from the transistor QP9 is I.sub.C(QP8) +I.sub.B(QP10) (I.sub.B is the base current), in which the parameter to control the fall time tf is only I.sub.B(QP10). The discharge of I.sub.B(QP10) by the transistor being on is simply like a switch being on adjustment of tf to be suitable is significantly difficult. Even if such a difficult adjustment is performed, the set value of the resistor RP3 or the constant current circuit 1 is restricted, causing a problem such that simultaneous setting of tr and tf to a suitable value in the circuit of this example is impossible.
Actually, the output waveforms in the rise and fall times of the output in FIG. 8 are like what are shown by the curves b.sub.H and b.sub.L in FIGS. 9 and 10 respectively (a.sub.H and a.sub.L in the figures are an X input waveform respectively in the rise and fall times of the output). As shown in the figures, the slew rates at the rise and fall times are respectively 0.910 V/nsec and 2.660 V/nsec; however, in comparison with, for example, the slew rate standard 0.65 V/nsec (the maximum slew rate at the rise and fall times of the output, shown in broken lines in the figures) defined as the signal transmission speed 4.5 Mbps version standard in a computer system, these rates are proven to be too large (this causes a false operation as described above). The output waveforms b.sub.H and b.sub.L in FIGS. 9 and 10 are shown for three cases, each with the power supply voltage V.sub.CC being 5.25 (V), 5.0 (V), and 4.75 (V) respectively.